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1 of 16 rev: 110805 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . features real-time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap-year compensation valid up to 2100 31 x 8 ram for scratchpad data storage serial i/o for minimum pin count 2.0v to 5.5v full operation uses less than 300na at 2.0v single-byte or multiple-byte (burst mode) data transfer for read or write of clock or ram data 8-pin dip or optional 8-pin so for surface mount simple 3-wire interface ttl-compatible (v cc = 5v) optional industrial temperature range: -40c to +85c ds1202 compatible underwriters laboratory (ul) recognized pin configurations ordering information part temp range pin-package top mark* ds1302 0c to +70c 8 pdip (300 mils) ds1302 ds1302+ 0c to +70c 8 pdip (300 mils) ds1302 ds1302n -40c to +85c 8 pdip (300 mils) ds1302 ds1302n+ -40c to +85c 8 pdip (300 mils) ds1302 ds1302s 0c to +70c 8 so (208 mils) ds1302s ds1302s+ 0c to +70c 8 so (208 mils) ds1302s ds1302sn -40c to +85c 8 so (208 mils) ds1302s ds1302sn+ -40c to +85c 8 so (208 mils) ds1302s ds1302z 0c to +70c 8 so (150 mils) ds1302z ds1302z+ 0c to +70c 8 so (150 mils) ds1302z ds1302zn -40c to +85c 8 so (150 mils) ds1302zn ds1302zn+ -40c to +85c 8 so (150 mils) ds1302zn ds1302s-16 0c to +70c 16 so (300 mils) ds1302s16 ds1302sn-16 -40c to +85c 16 so (300 mils) ds1302sn16 + denotes a lead-free/rohs-compliant device. *an n anywhere on the top mark indicates an industrial temperature grade device. a + anywhere on the top ma rk indicates a lead-free device. ds1302 trickle-charge timekeeping chip www.maxim-ic.com v cc1 sclk i/o ce v cc2 x1 x2 gnd 8 7 6 5 1 2 3 4 d ip ( 300 mils) ds1302 v cc2 x1 x2 gnd v cc1 sclk i/o ce 8 7 6 5 1 2 3 4 so (208 mils/150 mils) ds1302 v cc2 x1 x2 gnd i/o n.c. n.c. ce 12 11 10 9 5 6 7 8 so (300 mils) 1 2 3 4 v cc1 n.c. sclk n.c. 16 15 14 13 n.c. n.c. n.c. n.c. ds1302 top view
ds1302 trickle-charge timekeeping chip 2 of 16 detailed description the ds1302 trickle-charge timekeeping chip contains a real-time clock/cale ndar and 31 bytes of static ram. it communicates with a microprocessor via a simple serial inte rface. the real-time clock/ca lendar provides seconds, minutes, hours, day, date, month, and y ear information. the end of the mont h date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with an am/pm indicator. interfacing the ds1302 with a microprocessor is simplifi ed by using synchronous serial communication. only three wires are required to communicate with the clock/ram: ce, i/o (data line), and sclk (serial clock). data can be transferred to and from the clock/ram 1 byte at a time or in a burst of up to 31 bytes. the ds1302 is designed to operate on very low power and retain data and clock information on less than 1 w. the ds1302 is the successor to the ds1202. in addition to the basic timekeeping functions of the ds1202, the ds1302 has the additional features of dual power pins for primary and backup power supplies, programmable trickle charger for v cc1 , and seven additional bytes of scratchpad memory. operation figure 1 shows the main elements of the serial timekeeper: sh ift register, control logic, oscillator, real-time clock, and ram. typical operating circuit ds1302 cpu v cc v cc2 sclk ce gnd x2 x1 v cc i/o v cc1
ds1302 trickle-charge timekeeping chip 3 of 16 figure 1. block diagram typical operating characteristics (v cc = 3.3v, t a = +25c, unless otherwise noted.) power control v cc1 v cc 2 gnd input shift registers i/o sclk command and control logic real-time clock 31 x 8 ram oscillator a nd countdown chain x1 x2 ce 1hz ds1302 i cc2t vs. v cc2t 5 10 15 20 25 30 2.03.04.05.0 v cc2 (v) supply current (ua ) i cc1t vs. v cc1t 100 150 200 250 300 350 400 2.0 3.0 4.0 5.0 v cc1 (v) supply current (na )
ds1302 trickle-charge timekeeping chip 4 of 16 pin description pin 8 16 name function 1 1 v cc2 primary power-supply pin in dual supply configuration. v cc1 is connected to a backup source to maintain the time and date in the absence of primary power. the ds1302 operates from the larger of v cc1 or v cc2 . when v cc2 is greater than v cc1 + 0.2v, v cc2 powers the ds1302. when v cc2 is less than v cc1 , v cc1 powers the ds1302. 2 3 x1 3 5 x2 connections for standard 32.768khz quartz crystal. the internal oscillator is designed for operation with a crystal havi ng a specified load capacitance of 6pf. for more information on crystal selection and crystal layout considerations, refer to application note 58: crystal considerations for dallas real-time clocks . the ds1302 can also be driven by an exte rnal 32.768khz oscillator. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. 4 8 gnd ground 5 9 ce input. ce signal must be asserted high during a read or a write. this pin has an internal 40k ? (typ) pulldown resistor to ground. note: previous data sheet revisions referred to ce as rst . the functionality of the pin has not changed. 6 12 i/o input/push-pull output. the i/o pin is t he bidirectional data pin for the 3-wire interface. this pin has an internal 40k ? (typ) pulldown resistor to ground. 7 14 sclk input. sclk is used to synchronize data move ment on the serial interface. this pin has an internal 40k ? (typ) pulldown resistor to ground. 8 16 v cc1 low-power operation in single supply and battery-operated systems and low- power battery backup. in systems using the trickle charger, the rechargeable energy source is connected to this pin. ul recognized to ensure against reverse charging current when used with a lithium battery. ? 2, 4, 6, 7, 10, 11, 13, 15 n.c. no connection
ds1302 trickle-charge timekeeping chip 5 of 16 oscillator circuit the ds1302 uses an external 32.768khz crystal. the oscillat or circuit does not require any external resistors or capacitors to operate. table 1 specifies several crysta l parameters for the external crystal. figure 2 shows a functional schematic of the os cillator circuit. if using a crysta l with the specified characteri stics, the startup time is usually less than one second. clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capa citive load for which the crystal was trimmed. additional error will be added by crystal frequency drift caused by tem perature shifts. external circuit noise coupled into the oscillator circuit may result in the clock running fast. fi gure 3 shows a typical pc boar d layout for isolating the crystal and oscillator from noise. refer to application note 58: crystal consider ations for dallas real-time clocks for detailed information. table 1. crystal specifications* parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 6 pf *the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for additional s pecifications. figure 2. oscillator circuit s howing internal bias network figure 3. typical pc bo ard layout for crystal countdown chain rtc x1 x2 crystal c l 1 c l 2 rtc registers local ground plane (layer 2) crystal x1 x2 gnd note: a void routing signals in the crosshatched area (upper left- hand quadrant) of the package unless there is a ground plane between the signal line and the package.
ds1302 trickle-charge timekeeping chip 6 of 16 command byte figure 4 shows the command byte. a command byte initiates each data transfer. the msb (bit 7) must be a logic 1. if it is 0, writes to the ds1302 will be disabled. bit 6 spec ifies clock/calendar data if l ogic 0 or ram data if logic 1. bits 1 to 5 specify the designated registers to be input or output, and the lsb (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. the command byte is always input starting with the lsb (bit 0). figure 4. address/command byte ce and clock control driving the ce input high initiates all data transfers. t he ce input serves two functions. first, ce turns on the control logic that allows access to the shift register for the address/command sequence. second, the ce signal provides a method of terminating either singl e-byte or multiple-byte ce data transfer. a clock cycle is a sequence of a rising edge followed by a falling edge. for data inputs, data must be valid during the rising edge of the clock and data bits are output on t he falling edge of clock. if the ce input is low, all data transfer terminates and the i/o pin goes to a high-impedance state. figure 5 shows data transfer. at power-up, ce must be a logic 0 until v cc > 2.0v. also, sclk must be at a logic 0 when ce is driven to a logic 1 state. data input following the eight sclk cycles that input a write command byte, a data byte is input on the rising edge of the next eight sclk cycles. additional sclk cycles are ignored shoul d they inadvertently occur. data is input starting with bit 0. data output following the eight sclk cycles that in put a read command byte, a data byte is output on the falling edge of the next eight sclk cycles. note that the first data bit to be tr ansmitted occurs on the first falling edge after the last bit of the command byte is written. additi onal sclk cycles retransmit the data bytes should they inadvertently occur so long as ce remains high. this operation permits contin uous burst mode read capability. also, the i/o pin is tri- stated upon each rising edge of sclk. data is output starting with bit 0. burst mode burst mode can be specified for either the clock/calendar or the ram registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). as before, bit 6 specifies clock or ram and bit 0 specifies read or write. there is no data storage capaci ty at locations 9 through 31 in the clock/calendar registers or location 31 in the ram registers. reads or writes in burst mode start with bit 0 of address 0. when writing to the clock registers in the burst mode, the fi rst eight registers must be written in order for the data to be transferred. however, when writing to ram in burst mode it is not necessary to write all 31 bytes for the data to transfer. each byte that is written to will be transferred to ram regardless of whether all 31 bytes are written or not. clock/calendar the time and calendar information is obtained by reading the appropriate register bytes. table 2 illustrates the rtc registers. the time and calendar are set or initialized by writing the appropriate register bytes. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. 1 ram ck a4 a3 a2 a1 a0 rd wr 76543210
ds1302 trickle-charge timekeeping chip 7 of 16 the day-of-week register increments at midnight. values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on.). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, seco ndary (user) buffers are used to prevent errors when the internal registers update. when reading the time and dat e registers, the user buffe rs are synchronized to the internal registers the rising edge of ce. the countdown chain is reset whenever the seconds register is written. write transfers occur on the falling edge of ce. to avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. the ds1302 can be run in either 12-hour or 24-hour mode. bit 7 of the hours register is defined as the 12- or 24- hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/ pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20?23 hours ). the hours data must be re-initialized whenever the 12/ 24 bit is changed. clock halt flag bit 7 of the seconds register is defined as the clock halt (ch) flag. when this bit is set to logic 1, the clock oscillator is stopped and the ds1302 is placed into a low-power stand by mode with a current drain of less than 100na. when this bit is written to logic 0, the clock will start. the initial power- on state is not defined. write-protect bit bit 7 of the control register is the writ e-protect bit. the first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. before any write operation to the clock or ram, bit 7 must be 0. when high, the write-protect bit prevents a write operation to any other register. the init ial power-on state is not defined. therefore, the wp bit should be cleared before attemp ting to write to the device. trickle-charge register this register controls the trickle-c harge characteristics of the ds1302. the simplified schematic of figure 6 shows the basic components of the trickle charge r. the trickle-charge select (tcs) bits (bits 4 to 7) control the selection of the trickle charger. to prevent accide ntal enabling, only a pattern of 1010 en ables the trickle charger. all other patterns will disable the trickle charger . the ds1302 powers up with the trickle charger disabled. the diode select (ds) bits (bits 2 and 3) select whether one diode or two diodes are connected between v cc2 and v cc1 . if ds is 01, one diode is selected or if ds is 10, two diodes are sele cted. if ds is 00 or 11, the trickle charger is disabled independently of tcs. the rs bits (bits 0 and 1) select the resistor that is connected between v cc2 and v cc1 . the resistor selected by the resistor select (rs) bits is as follows: rs bits resistor typical value 00 none none 01 r1 2k ? 10 r2 4k ? 11 r3 8k ? if rs is 00, the trickle charger is disabled independently of tcs. diode and resistor selection is determined by the user ac cording to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a system power su pply of 5v is applied to v cc2 and a super cap is connected to v cc1 . also assume that the trickle charger has been enabled with one diode and resistor r1 between v cc2 and v cc1 . the maximum current i max would therefore be calculated as follows: i max = (5.0v ? diode drop) / r1 (5.0v ? 0.7v) / 2k ? 2.2ma as the super cap charges, the voltage drop between v cc2 and v cc1 decreases and therefore the charge current decreases.
ds1302 trickle-charge timekeeping chip 8 of 16 clock/calendar burst mode the clock/calendar command byte specifies burst mode oper ation. in this mode, the first eight clock/calendar registers can be consecut ively read or written (see table 2) starting with bit 0 of address 0. if the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the c ontrol register). the trickle charger is not accessible in burst mode. at the beginning of a clock burst read, the current time is transferred to a second se t of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re-read the registers in case of an updat e of the main registers during a read. ram the static ram is 31 x 8 bytes addressed consecutively in t he ram address space. ram burst mode the ram command byte specifies burst m ode operation. in this mode, the 31 ram registers can be consecutively read or written (see table 2) starting with bit 0 of address 0. register summary a register data format summary is shown in table 2. crystal selection a 32.768khz crystal can be directly conne cted to the ds1302 via pins 2 and 3 (x1, x2). the crystal selected for use should have a specified load capacitance (c l ) of 6pf. for more information on crystal selection and crystal layout consideration, refer to application note 58: crystal considerations for dallas real-time clocks . figure 5. data transfer summary a1 a2 a3 a4 r/ c 1 ce sclk i/o r/ w a0 d1 d2 d3 d4 d5 d6 d7 d0 single-byte read a1 a2 a3 a4 r/ c 1 ce sclk i/o r/ w a0 d1 d2 d3 d4 d5 d6 d7 d0 single-byte write note: in burst mode, ce is kept high and additional sclk cycles are sent until the end of the burst.
ds1302 trickle-charge timekeeping chip 9 of 16 table 2. register address/definition rtc read write bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 range 81h 80h ch 10 seconds seconds 00?59 83h 82h 10 minutes minutes 00?59 10 85h 84h 12/ 24 0 am /pm hour hour 1?12/0?23 87h 86h 0 0 10 date date 1?31 89h 88h 0 0 0 10 month month 1?12 8bh 8ah 0 0 0 0 0 day 1?7 8dh 8ch 10 year year 00?99 8fh 8eh wp 0 0 0 0 0 0 0 ? 91h 90h tcs tcs tcs tcs ds ds rs rs ? clock burst bfh beh ram c1h c0h 00-ffh c3h c2h 00-ffh c5h c4h 00-ffh . . . . . . . . . fdh fch 00-ffh ram burst ffh feh figure 6. programmable trickle charger 2k ? 4k ? 8k ? r1 r3 r2 v cc2 v cc1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charge register (90h write, 91h read) 1 0f 16 select note: only 1010b enables charger 1 of 2 select 1 of 3 select tcs 0-3 = trickle charger select ds 0-1 = diode select rout 0-1 = resistor select
ds1302 trickle-charge timekeeping chip 10 of 16 absolute maximum ratings voltage range on any pin relative to ground????????????????????????.-0.5vto +7.0v operating temperature ra nge, commercial?????????????????????????.0c to +70c operating temperature range, industrial (ind)???????????????????????-40c to +85c storage temperature range?????????????????????????????..?.-55c to +125c soldering temperature (leads, 10 seconds)????????????????????????..????.260c soldering temperature (surface mount)?? ????????????????..??.see ipc/jedec j-std-020 stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating condi tions for extended periods may affect device reliability. recommended dc op erating conditions (t a = 0c to +70c or t a = -40c to +85c.) (note 1) parameter symbol conditions min typ max units supply voltage v cc1 , v cc2 v cc1, v cc2 (notes 2, 10) 2.0 3.3 5.5 v logic 1 input v ih (note 2) 2.0 v cc + 0.3 v v cc = 2.0v -0.3 +0.3 logic 0 input v il v cc = 5v (note 2) -0.3 +0.8 v dc electrical characteristics (t a = 0c to +70c or t a = -40c to +85c.) (note 1) parameter symbol conditions min typ max units input leakage i li (notes 5, 13) 85 500 a i/o leakage i lo (notes 5, 13) 85 500 a logic 1 output (i oh = -0.4ma) v cc = 2.0v 1.6 logic 1 output (i oh = -1.0ma) v oh v cc = 5v (note 2) 2.4 v logic 0 output (i ol = 1.5ma) v cc = 2.0v 0.4 logic 0 output (i ol = 4.0ma) v ol v cc = 5v (note 2) 0.4 v v cc1 = 2.0v 0.4 active supply current (oscillator enabled) i cc1a v cc1 = 5v ch = 0 (notes 4, 11) 1.2 ma v cc1 = 2.0v 0.2 0.3 timekeeping current (oscillator enabled) i cc1t v cc1 = 5v ch = 0 (notes 3, 11,13) 0.45 1 a v cc1 = 2.0v 1 100 v cc1 = 5v 1 100 standby current (oscillator disabled) i cc1s ind ch = 1 (notes 9, 11, 13) 5 200 na v cc2 = 2.0v 0.425 active supply current (oscillator enabled) i cc2a v cc2 = 5v ch = 0 (notes 4, 12) 1.28 ma v cc2 = 2.0v 25.3 timekeeping current (oscillator enabled) i cc2t v cc2 = 5v ch = 0 (notes 3, 12) 81 a v cc2 = 2.0v ch = 1 (notes 9, 12) 25 standby current (oscillator disabled) i cc2s v cc2 = 5v 80 a r1 2 r2 4 trickle-charge resistors r3 8 k ? trickle-charge diode voltage drop v td 0.7 v
ds1302 trickle-charge timekeeping chip 11 of 16 capacitance (t a = +25c) parameter symbol min typ max units input capacitance c i 10 pf i/o capacitance c i/o 15 pf ac electrical characteristics (t a = 0c to +70c or t a = -40c to +85c.) (note 1) parameter symbol conditions min typ max units v cc = 2.0v 200 data to clk setup t dc v cc = 5v (note 6) 50 ns v cc = 2.0v 280 clk to data hold t cdh v cc = 5v (note 6) 70 ns v cc = 2.0v 800 clk to data delay t cdd v cc = 5v (notes 6, 7, 8) 200 ns v cc = 2.0v 1000 clk low time t cl v cc = 5v (note 6) 250 ns v cc = 2.0v 1000 clk high time t ch v cc = 5v (note 6) 250 ns v cc = 2.0v 0.5 clk frequency t clk v cc = 5v (note 6) dc 2.0 mhz v cc = 2.0v 2000 clk rise and fall t r , t f v cc = 5v 500 ns v cc = 2.0v 4 ce to clk setup t cc v cc = 5v (note 6) 1 s v cc = 2.0v 240 clk to ce hold t cch v cc = 5v (note 6) 60 ns v cc = 2.0v 4 ce inactive time t cwh v cc = 5v (note 6) 1 s v cc = 2.0v 280 ce to i/o high impedance t cdz v cc = 5v (note 6) 70 ns v cc = 2.0v 280 sclk to i/o high impedance t ccz v cc = 5v (note 6) 70 ns note 1: limits at -40c are guaranteed by des ign and are not production tested. note 2: all voltages are referenced to ground. note 3: i cc1t and i cc2t are specified with i/o open, ce and sclk set to a logic 0. note 4: i cc1a and i cc2a are specified with the i/o pin open, ce high, sclk = 2mhz at v cc = 5v; sclk = 500khz, v cc = 2.0v. note 5: ce, sclk, and i/o all have 40k ? pulldown resistors to ground. note 6: measured at v ih = 2.0v or v il = 0.8v and 10ns maximum rise and fall time. note 7: measured at v oh = 2.4v or v ol = 0.4v. note 8: load capacitance = 50pf. note 9: i cc1s and i cc2s are specified with ce, i/o, and sclk open. note 10: v cc = v cc2 , when v cc2 > v cc1 + 0.2v; v cc = v cc1 , when v cc1 > v cc2 . note 11: v cc2 = 0v. note 12: v cc1 = 0v. note 13: typical values are at +25c.
ds1302 trickle-charge timekeeping chip 12 of 16 figure 7. timing diagram: read data transfer figure 8. timing diagram: write data transfer chip information transistor count: 11,500 thermal information package theta-ja (c/w) theta-jc (c/w) 8 dip 110 40 8 so (150 mils) 170 40 8 so (208 mils) 113 31 16 so (300 mils) 105 22 ce sclk i/o 1 dc t cdh t cc t a0 r/ w d0 d7 t cdz t cdd r t f t cl t ch t write command byte read data byte t ccz ce sclk i/o 0 dc t cdh t t cc a0 1 d7 t r t f t cl t cch cwh t write command byte write data byte t ch d0
ds1302 trickle-charge timekeeping chip 13 of 16 package information (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)
ds1302 trickle-charge timekeeping chip 14 of 16 package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)
ds1302 trickle-charge timekeeping chip 15 of 16 package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)
dsxxxx description 16 of 16 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. package information (continued) (the package drawing(s) in this data sheet may not reflect t he most current specifications . for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs ds1302 part number table notes: see the ds1302 quickview data sheet for further information on this product family or download the ds1302 full data sheet (pdf, 672kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1302 pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-7 * 0c to +70c rohs/lead-free: no materials analysis ds1302+ pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8+7 * 0c to +70c rohs/lead-free: yes materials analysis ds1302n+ pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8+7 * -40c to +85c rohs/lead-free: yes materials analysis ds1302n pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-7 * -40c to +85c rohs/lead-free: no materials analysis ds1302s-16 soic ;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-11 * 0c to +70c rohs/lead-free: no materials analysis ds1302s-16/t&r soic ;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-11 * 0c to +70c rohs/lead-free: no materials analysis ds1302sn-16 soic ;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-11 * -40c to +85c rohs/lead-free: no materials analysis
ds1302sn-16/t&r soic ;16 pin;300 dwg: 56-g4009-001b (pdf) use pkgcode/variation: w16-11 * -40c to +85c rohs/lead-free: no materials analysis ds1302z+t&r soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * 0c to +70c rohs/lead-free: yes materials analysis ds1302z+ soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * 0c to +70c rohs/lead-free: yes materials analysis ds1302z/t&r soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * 0c to +70c rohs/lead-free: no materials analysis ds1302s+ soic ;8 pin;208 dwg: 56-g4010-001b (pdf) use pkgcode/variation: w8+3 * 0c to +70c rohs/lead-free: yes materials analysis ds1302z soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * 0c to +70c rohs/lead-free: no materials analysis ds1302s/t&r soic ;8 pin;208 dwg: 56-g4010-001b (pdf) use pkgcode/variation: w8-3 * 0c to +70c rohs/lead-free: no materials analysis ds1302s soic ;8 pin;208 dwg: 56-g4010-001b (pdf) use pkgcode/variation: w8-3 * 0c to +70c rohs/lead-free: no materials analysis ds1302s+t&r soic ;8 pin;208 dwg: 56-g4010-001b (pdf) use pkgcode/variation: w8+3 * 0c to +70c rohs/lead-free: yes materials analysis ds1302zn+t&r soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+2 * -40c to +85c rohs/lead-free: yes materials analysis ds1302sn+ soic ;8 pin;208 dwg: 56-g4010-001b (pdf) use pkgcode/variation: w8+3 * -40c to +85c rohs/lead-free: yes materials analysis ds1302zn+ soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+2 * -40c to +85c rohs/lead-free: yes materials analysis ds1302zn/t&r soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis ds1302zn soic ;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis ds1302sn/t&r soic ;8 pin;208 dwg: 56-g4010-001b (pdf) use pkgcode/variation: w8-3 * -40c to +85c rohs/lead-free: no materials analysis ds1302sn soic ;8 pin;208 dwg: 56-g4010-001b (pdf) use pkgcode/variation: w8-3 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need?
ds1302sn+t&r soic ;8 pin;208 dwg: 56-g4010-001b (pdf) use pkgcode/variation: w8+3 * -40c to +85c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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